Synchronized Transitions

Resumé

This paper presents a high-level notation for designing a VLSI chip as a number of asynchronous state machines. The machines are asynchronous in that they make state transitions without reference to a common time standard such as a common clock. The notation allows high-level descriptions of the functional behavior of an electrical circuit. This makes it possible to explore and verify different design decisions at a very early stage of the design, before making a detailed implementation. By imposing certain constraints on the abstract description, it is possible to transform it into a layout or program by using so-called implementation rules.