Efficient Timed Reachability Analysis using Clock Difference Diagrams

  • Gerd Behrmann
  • Kim G. Larsen
  • Justin Pearson
  • Carsten Weise
  • Wang Yi


One of the major problems in applying automatic verication tools to industrial-size systems is the excessive amount of memory required during the state-space exploration of a
model. In the setting of real-time, this problem of state-explosion requires extra attention as information must be kept not only on the discrete control structure but also on the values of continuous clock variables. In this paper, we present Clock Dierence Diagrams, CDD's, a BDD-like data-structure for
representing and eectively manipulating certain non-convex subsets of the Euclidean space, notably those encountered during verication of timed automata. A version of the real-time verication tool Uppaal using CDD's as a compact datastructure
for storing explored symbolic states has been implemented. Our experimental results demonstrate signicant space-savings: for 8 industrial examples, the savings are between 46%
and 99% with moderate increase in runtime. We further report on how the symbolic state-space exploration itself may be carried out using CDD's.
How to Cite
Behrmann, G., Larsen, K., Pearson, J., Weise, C., & Yi, W. (1998). Efficient Timed Reachability Analysis using Clock Difference Diagrams. BRICS Report Series, 5(47). https://doi.org/10.7146/brics.v5i47.19492